1. Field of the Invention
The present invention relates generally to semiconductor fabrication and more particularly, to a method of optimizing a pattern of semiconductor devices, particularly Integrated Circuit (IC) chips, on a photoresist-coated semiconductor wafer onto which the semiconductor chips are imprinted by means of a mask.
2. Description of the Prior Art
A method for optimizing a pattern of semiconductor chips on a wafer is disclosed in DE 32 47 141. This method takes into account the problem that a wafer has particular areas onto which no semiconductor chips are to be imprinted. Such areas commonly serve to imprint test patterns, which are desirable for the manufacturer or are needed in order to align the exposure equipment. To reduce the loss of wafer area in the region around these test patterns, the patterns to be imprinted, i.e., the step fields, are varied relative to each other so that no empty areas will remain around the areas to be kept free.
There are processes which involve the fabrication of a mask by means of which the full chip pattern on the wafer is exposed at once. In other processes, a mask comprises a step field of semiconductor chips. In that case, use is made of a stepper with which the step fields, containing a given number of semiconductor chips, are imprinted onto the wafer in a step-and-repeat fashion by means of the mask. After that, the photoresist is developed. This is followed by a predetermined process, such as etching or ion implantation. After this process step, the photoresist material is removed from the wafer, which completes the first patterning step of the semiconductor fabrication process. In the same manner, further patterning steps are performed, in which the mask for producing the step field pattern must be aligned like the corresponding mask in the first patterning step. The mask used in the first patterning step is commonly aligned so that its longitudinal axis coincides with the longitudinal axis of the wafer and that it is moved in the direction of the longitudinal axis so as not to overlap the wafer areas to be exposed.
It is therefore, an object of the present invention to provide a method whereby the fabrication costs per semiconductor chip is reduced.